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data sheet MPC9230 revision 8 march 29, 2010 1 ?2010 integrated device technology, inc. 800mhz low voltage pecl clock synthesizer MPC9230 the MPC9230 is a 3.3 v compatible, pll based clock synthesizer targeted for high perfor- mance clock generation in mid-range to high-pe rformance telecom, networking and computing applications. with output frequ encies from 50 mhz to 800 mhz (1) and the support of differential pecl output signals the device meets the needs of the most demanding clock applications. features ? 50 mhz to 800 mhz (1) synthesized clock output signal ? differential pecl output ? lvcmos compatible control inputs ? on-chip crystal oscillator for reference frequency generation ? alternative lvcmos compatible reference clock input ? 3.3 v power supply ? fully integrated pll ? minimal frequency overshoot ? serial 3-wire programming interface ? parallel programming interface for power-up ? 32-lead lqfp and 28-lead plcc packaging ? 32-lead and 28-lead pb-free package available ? sige technology ? ambient temperature range -40 c to +85 c ? pin and function compatible to the mc12430 functional description the internal crystal oscillator uses the external quartz crystal as the basis of its frequency reference. the frequency of the internal crystal oscillator is divided by 16 and then mult iplied by the pll. the vco within the pll operates over a range of 800 to 1600 mhz. (1) its output is scaled by a divider that is configured by either the serial or parallel interfaces. the crystal oscillator frequency f xtal , the pll feedback-divider m and the pll post-divider n determine the output frequency. the feedback path of the pll is internal. the pll adjusts the vc o output frequency to be m/4 time s the external input reference frequency. note that for some values of m (either too high or too low) the pll will not achieve phase lock. the pll will be stable if the vco frequency is within the specified vco frequency range (800 to 1600 mhz (1) ). the m-value must be programmed by the serial or parallel interface. the pll post-divider n is configured through either the serial or the parallel interfaces, and can provide one of four division ratios (1, 2, 4, or 8). this divider extends performance of the part while provid ing a 50% duty cycle. the output driver is driven differentiall y from the output divider, and is capable of driving a pair of transmission lines terminated 50 ? to v cc ? 2.0 v. the positive supply voltage for the internal pll is separated from the power supply for the core logic and output drivers to minimize noise induced jitter. the configuration logic has two sections: serial and parallel. the parallel interface uses the values at the m[8:0] and n[1:0] inputs to configure the internal counters. it is recommend ed on system reset to hold the p_load input low until power become s valid. on the low-to-high transition of p_load , the parallel inputs are captured. the parallel interface has prio rity over the serial interface. internal pullup resistors ar e provided on the m[8:0] and n[1:0] inpu ts and prevent the lvcmos compatible control inputs from floating. the serial interface centers on a fourteen bit shift register. the shift register shifts once per rising edge of the s_clock in put. the serial input s_data must meet setup and hold timing as specified in th e ac characteristics section of this document. the configuration latches will capture the value of the shift re gister on the high-to-low edge of the s_load inpu t. see the programming section for more infor mation. the test output reflects various internal node values, and is contro lled by the t[2:0] bits in the serial data stream. in order to minimize the pll jitter, it is recommended to avoid active signal on the test output. 1. the vco frequency range of 800?1600 mhz is available at an ambient temperature range of 0 to 70c. at ?40 to +85c, the vco f requency (output frequency) is limited to max. 1500 mhz (750 mhz). MPC9230 800 mhz low voltage clock synthesizer fn suffix 28-lead plcc package case 776-02 fa suffix 32-lead lqfp package case 873a-04 ei suffix 28-lead plcc package pb-free package case 776-02 ac suffix 32-lead lqfp package pb-free package case 873a-04
MPC9230 revision 8 march 29, 2010 2 ?2010 integrated device technology, inc. MPC9230 data sheet 800mhz low voltage pecl clock synthesizer figure 1. MPC9230 logic diagram figure 2. MPC9230 28-lead plcc pinout (top view) figure 3. MPC9230 32-lead package pinout (top view) xtal_in xtal_out s_load s_data s_clock m[0:8] xtal pll ref fb vco 800 ?? 1600 m 11 00 01 10 9-bit m-divider m-latch n-latch 10 ?? 20 m t-latch 9 2 test 3 le 01 01 bits 5-13 bits 3-4 bits 0-2 14-bit shift register n[1:0] oe p/s 1 2 4 8 fout test oe fref_ext xtal_sel p_load f out v cc v cc v cc ? 1 ? ? 0 to ? 5 ? 1 4 3 2 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 78 6 5 v cc xtal_out p_load oe m[0] m[1] m[2] m[3] fout gnd v cc test gnd s_clock n[1] n[0] m[8] m[7] m[6] m[5] m[4] s_data s_load v cc_pll fref_ext xtal_sel xtal_in MPC9230 f out gnd test v cc v cc gnd fout nc m[3] m[2] m[1] m[0] p_load nc n[1] n[0] m[8] m[7] m[6] m[5] m[4] s_clock s_load v cc_pll v cc_pll fref_ext xtal_sel xtal_in 25 26 27 28 29 30 31 32 15 14 13 12 11 10 9 12345678 24 23 22 21 20 19 18 17 16 v cc oe xtal_out s_data MPC9230 f out
MPC9230 revision 8 march 29, 2010 3 ?2010 integrated device technology, inc. MPC9230 data sheet 800mhz low voltage pecl clock synthesizer table 1. pin configurations pin i/o default type function xtal_in, xtal_out analog crystal oscillator interface fref_ext input 0 lvcmos alternative pll reference input f out , f out output lvpecl differential clock output test output lvpecl test and device diagnosis output xtal_sel input 1 lvcmos pll reference select input s_load input 0 lvcmos serial configuration control input this input controls the loading of the configuratio n latches with the contents of the shift register. the latches will be transparent when this signal is high, thus the data must be stable on the high-to-low transition. p_load input 1 lvcmos parallel configuration control input. this input controls the loading of the configurati on latches with the content of the parallel inputs (m and n). the latches will be transparent when this signal is low, thus the parallel data must be stable on the low-to-high transition of p_load . p_load is state sensitive. s_data input 0 lvcmos serial configuration data input s_clock input 0 lvcmos serial configuration clock input m[0:8] input 1 lvcmos parallel configuration fo r pll feedback divider (m). m is sampled on the low-to-high transition of p_load n[1:0] input 1 lvcmos parallel configuration for post-pll divider (n). n is sampled on the low-to-high transition of p_load oe input 1 lvcmos output enable (active high) the output enable is synchronous to the output clock to eliminate the possibility of runt pulses on the f out output gnd supply ground negative power supply (gnd) v cc supply v cc positive power supply for i/o and core. all v cc pins must be connected to the positive power supply for correct operation v cc_pll supply v cc pll positive power suppl y (analog power supply) table 2. output frequency range and pll post-divider n n output division output frequency range for t a = 0c to +70c output frequency range for t a = ?40c to +85c 1 0 0 0 2 200 ? 400 mhz 200 ? 375 mhz 0 1 4 100 ? 200 mhz 100 ? 187.5 mhz 1 0 8 50 ? 100 mhz 50 ? 93.75 mhz 1 1 1 400 ? 800 mhz 400 ? 750 mhz table 3. function table input 0 1 xtal_sel fref_ext xtal interface oe outputs disabled. f out is stopped in the logic low state (f out = l, f out = h) outputs enabled
MPC9230 revision 8 march 29, 2010 4 ?2010 integrated device technology, inc. MPC9230 data sheet 800mhz low voltage pecl clock synthesizer table 4. general specifications symbol characteristics min typ max unit condition v tt output termination voltage v cc ? 2 v mm esd protection (machine model) 200 v hbm esd protection (human body model) 2000 v lu latch-up immunity 200 ma c in input capacitance 4.0 pf inputs ja lqfp 32 thermal resistance junction to ambient jesd 51-3, single layer test board jesd 51-6, 2s2p multilayer test board 83.1 73.3 68.9 63.8 57.4 59.0 54.4 52.5 50.4 47.8 86.0 75.4 70.9 65.3 59.6 60.6 55.7 53.8 51.5 48.8 c/w c/w c/w c/w c/w c/w c/w c/w c/w c/w natural convection 100 ft/min 200 ft/min 400 ft/min 800 ft/min natural convection 100 ft/min 200 ft/min 400 ft/min 800 ft/min jc lqfp 32 thermal resistance junction to case 23.0 26.3 c/w mil-spec 883e method 1012.1 table 5. absolute maximum ratings (1) 1. absolute maximum continuous ratings are those maximum values beyond which damage to the device may occur. exposure to these c onditions or conditions beyond those indicated may adverse ly affect device reliability. functional operation at absolute-maximum-rated condi tions is not implied. symbol characteristics min max unit condition v cc supply voltage ?0.3 4.6 v v in dc input voltage ?0.3 v cc + 0.3 v v out dc output voltage ?0.3 v cc + 0.3 v i in dc input current 20 ma i out dc output current 50 ma t s storage temperature ?65 125 c table 6. dc characteristics (v cc = 3.3 v 5%, t a = 0c to +70c) symbol characteristics min typ max unit condition lvcmos control inputs (fref_ext, xtal_sel, p_load , s_load, s_data, s_clock, m[0:8], n[0:1]. oe) v ih input high voltage 2.0 v cc + 0.3 v lvcmos v il input low voltage 0.8 v lvcmos i in input current (1) 1. inputs have pull-down resistors affecting the input current. 200 a v in = v cc or gnd differential clock output f out (2) 2. outputs terminated 50 ? to v tt = v cc ? 2 v. v oh output high voltage v cc ?1.02 v cc ?0.74 v lvpecl v ol output low voltage v cc ?1.95 v cc ?1.60 v lvpecl test and diagnosis output test v oh output high voltage v cc ?1.02 v cc ?0.74 v lvpecl v ol output low voltage v cc ?1.95 v cc ?1.60 v lvpecl supply current i cc_pll maximum pll supply current 20 ma v cc_pll pins i cc maximum supply current 110 ma all v cc pins
MPC9230 revision 8 march 29, 2010 5 ?2010 integrated device technology, inc. MPC9230 data sheet 800mhz low voltage pecl clock synthesizer table 7. ac characteristics (v cc = 3.3 v 5%, t a = ?40c to +85c) symbol characteristics min typ max unit condition lvcmos control inputs (fref_ext, xtal_sel, p_load , s_load, s_data, s_clock, m[0:8], n[0:1]. oe) v ih input high voltage 2.0 v cc + 0.3 v lvcmos v il input low voltage 0.8 v lvcmos i in input current (1) 1. inputs have pull-down resistors affecting the input current. 200 a v in = v cc or gnd differential clock output f out (2) 2. outputs terminated 50 ? to v tt = v cc ? 2 v. v oh output high voltage v cc ?1.1 v cc ?0.74 v lvpecl v ol output low voltage v cc ?1.95 v cc ?1.65 v lvpecl test and diagnosis output test v oh output high voltage v cc ?1.1 v cc ?0.74 v lvpecl v ol output low voltage v cc ?1.95 v cc ?1.65 v lvpecl supply current i cc_pll maximum pll supply current 20 ma v cc_pll pins i cc maximum supply current 110 ma all v cc pins
MPC9230 revision 8 march 29, 2010 6 ?2010 integrated device technology, inc. MPC9230 data sheet 800mhz low voltage pecl clock synthesizer table 8. ac characteristics (v cc = 3.3 v 5%, t a = 0c to +70c) (1) 1. ac characteristics apply for parallel output termination of 50 ? to v tt . symbol characteristics min typ max unit condition f xtal crystal interface frequency range 10 20 mhz f ref fref_ext reference frequency range 10 (f vco,max m) ? 4 (2) 2. the maximum frequency on fref_ext is a function of the max. vco frequency and the m counter. m should be higher than 160 for stable pll operation. mhz f vco vco frequency range (3) 3. the input frequency f xtal and the pll feedback divider m must match the vco frequency range: f vco = f xtal ? m 4. 800 1600 mhz f max output frequency n = 11 ( 1) n = 00 ( 2) n = 01 ( 4) n = 10 ( 8) 400 200 100 50 800 400 200 100 mhz mhz mhz mhz f s_clock serial interface programming clock frequency (4) 4. the frequency of s_clock is limited to 10 mhz in serial programming mode. s_clock can be switched at higher frequencies when used as test clock in test mode 6. see applications information for more details. 0 10 mhz t p,min minimum pulse width (s_load, p_load) 50 ns dc output duty cycle 45 50 55 % t r , t f output rise/fall time 0.05 0.3 ns 20% to 80% t s setup time s_data to s_clock s_clock to s_load m, n to p_load 20 20 20 ns ns ns t h hold time s_data to s_clock m, n to p_load 20 20 ns ns t jit(cc) cycle-to-cycle jitter n = 11 ( 1) n = 00 ( 2) n = 01 ( 4) n = 10 ( 8) 30 35 45 55 80 90 130 160 ps ps ps ps t jit(per) period jitter n = 11 ( 1) n = 00 ( 2) n = 01 ( 4) n = 10 ( 8) 20 25 35 50 60 70 120 140 ps ps ps ps t lock maximum pll lock time 10 ms
MPC9230 revision 8 march 29, 2010 7 ?2010 integrated device technology, inc. MPC9230 data sheet 800mhz low voltage pecl clock synthesizer table 9. ac characteristics (v cc = 3.3 v 5%, t a = ?40c to +85c) (1) 1. ac characteristics apply for pa rallel output termination of 50 ? to v tt. symbol characteristics min typ max unit condition f xtal crystal interface frequency range 10 20 mhz f ref fref_ext reference frequency range 10 (f vco,max m)4 (2) 2. the maximum frequency on fref_ext is a function of the max. vco frequency and the m counter. m should be higher than 160 for stable pll operation. mhz f vco vco frequency range (3) 3. the input frequency f xtal and the pll feedback divider m must match the vco frequency range: f vco = f xtal ? m 4. 800 1500 mhz f max output frequency n = 11 ( 1) n = 00 ( 2) n = 01 ( 4) n = 10 ( 8) 400 200 100 50 750.00 375.00 187.50 93.75 mhz mhz mhz mhz f s_clock serial interface programming clock frequency (4) 4. the frequency of s_clock is limited to 10 mhz in serial programming mode. s_clock can be switched at higher frequencies when used as test clock in test mode 6. see applications information for more details. 0 10 mhz t p,min minimum pulse width (s_load, p_load) 50 ns dc output duty cycle 45 50 55 % t r , t f output rise/fall time 0.05 0.3 ns 20% to 80% t s setup time s_data to s_clock s_clock to s_load m, n to p_load 20 20 20 ns ns ns t h hold time s_data to s_clock m, n to p_load 20 20 ns ns t jit(cc) cycle-to-cycle jitter n = 11 ( 1) n = 00 ( 2) n = 01 ( 4) n = 10 ( 8) 30 35 45 55 80 90 130 160 ps ps ps ps t jit(cc) period jitter n = 11 ( 1) n = 00 ( 2) n = 01 ( 4) n = 10 ( 8) 20 25 35 50 60 70 120 140 ps ps ps ps t lock maximum pll lock time 10 ms
MPC9230 revision 8 march 29, 2010 8 ?2010 integrated device technology, inc. MPC9230 data sheet 800mhz low voltage pecl clock synthesizer programming interface programming the MPC9230 programming the MPC9230 amounts to properly configuring the internal pll dividers to produce the desired synthesized frequency at the output. the output frequen cy can be represented by this formula: f out = (f xtal 16) ? (4 ? m) (2 ? n) or (1) f out = (f xtal 8) ? m n(2) where f xtal is the crystal frequency, m is the pll feedback- divider and n is the pll post-divider. the input frequency and the selection of the feedback divider m is lim ited by the vco-frequency range. f xtal and m must be configured to match the vco frequency range of 800 to 1600 mhz in order to achieve stable pll operation: m min = 4 ? f vco,min f xtal and (3) m max = 4 ? f vco,max f xtal (4) for instance, the use of a 16 mhz input frequency requires the configuration of the pll feedback divider between m = 200 and m = 400. table 10 shows the usable vco frequency and m divider range for other example input frequencies. assuming that a 16 mhz input frequency is used, equation (2) reduces to: f out = 2 ? m n(5) table 10. MPC9230 frequency operating range vco frequency for an crystal interface frequency of [mhz] output frequency for f xtal =16 mhz and for n = m m[8:0] 10 12 14 16 18 20 1 2 4 8 160 010100000 800 170 010101010 850 180 010110100 810 900 190 010111110 855 950 200 011001000 800 900 1000 400 200 100 50 210 011010010 840 945 1050 420 210 105 52.5 220 011011100 880 990 1100 440 220 110 55 230 011100110 805 920 1035 1150 460 230 115 57.5 240 011110000 840 960 1080 1200 480 240 120 60 250 011111010 875 100 1125 1250 500 250 125 62.5 260 100000100 910 1040 1170 1300 520 260 130 65 270 100001110 810 945 1080 1215 1350 540 270 135 67.5 280 100011000 840 980 1120 1260 1400 560 280 140 70 290 100100010 870 1015 1160 1305 1450 580 290 145 72.5 300 100101100 900 1050 1200 1350 1500 600 300 150 75 310 100110110 930 1085 1240 1395 1550 (1) 1. this vco frequency is only available at the 0c to +70c temperature range. 620 310 155 77.5 320 101000000 800 960 1120 1280 1440 1600 (1) 640 320 160 80 330 101001010 825 990 1155 1320 1485 660 330 165 82.5 340 101010100 850 1020 1190 1360 1530 (1) 680 340 170 85 350 101011110 875 1050 1225 1400 1575 (1) 700 350 175 87.5 360 101101000 900 1080 1260 1440 720 360 180 90 370 101110010 925 1110 1295 1480 740 370 185 92.5 380 101111100 950 1140 1330 1520 (1) 760 (2) 2. this output frequency is only available at the 0c to +70c temperature range. 380 (2) 190 (2) 95 (2) 390 110000110 975 1170 1365 1560 (1) 780 (2) 390 (2) 195 (2) 97.5 (2) 400 110010000 1000 1200 1400 1600 (1) 800 (2) 400 (2) 200 (2) 100 (2) 410 110011010 1025 1230 1435 420 110100100 1050 1260 1470 430 110101110 1075 1290 1505 (1) 440 110111000 1100 1320 1540 (1) 450 111000010 1125 1350 1575 (1)
MPC9230 revision 8 march 29, 2010 9 ?2010 integrated device technology, inc. MPC9230 data sheet 800mhz low voltage pecl clock synthesizer substituting n for the four available values for n (1, 2, 4, 8) yields: example frequency calculation for an 16 mhz input frequency if an output frequency of 131 mhz was desired, the following steps would be taken to identify the appropriate m and n values. according to ta b l e 11 , 131 mhz falls in the frequency set by a value of 4, so n[1:0] = 01. for n = 4, the output frequency is f out = m 2 and m = f out x 2. therefore m = 2 x 131 = 262, so m[8:0] = 010000011. following this procedure a user can generate any whole frequency between 50 mhz and 800 mhz. note than for n > 2 fractional values of can be realized. the size of the programmable frequency steps (and thus the indicator of the fractional output frequencies achievable) will be equal to: f step = f xtal 8 n applications information using the parallel and serial interface the m and n counters can be loaded either through a parallel or serial interface. the parallel inte rface is controlled via the p_load signal such that a low to high tr ansition will latch the information present on the m[8:0] and n[1:0] inputs into the m and n counters. when the p_load signal is low, the input latches will be transparent and any changes on th e m[8:0] and n[ 1:0] inputs will affect the f out output pair. to use the serial port, the s_clock signal samples the information on the s_data line and loads it into a 14 bit shift register . note that the p_load signal must be high for the serial load operation to function. the test register is loaded with the first three bits, the n register with the next two and the m register with the final eight bits of the data stream on the s_data input. for each register the most si gnificant bit is loaded fi rst (t2, n1 and m8). a pulse on the s_load pin after the shift register is fully loaded will transfer the divide values into the counters. t he high to low transition on the s_load input will latch the new divide values into the counters. figure 4 illustrates the timing diagram for both a parallel and a serial load of th e MPC9230 synthesizer. m[8:0] and n[1:0] are normally specified onc e at power-up through the parallel interface, and then possibly again through the serial interface. this approach allows the application to come up at one frequency and then change or fine-tune the clock as the ability to control the serial interface becomes available. using the test and diagnosis output test the test output provides visibility for one of the several internal nodes as determined by the t[2:0] bits in the serial configuration stream. it is not configurable thro ugh the parallel interface. although it is possible to select the node that represents f out , the lvpecl compatible test output is not ab le to toggle fast enough for higher output frequencies and should only be used for test and diagnosis. the t2, t1 and t0 control bits are preset to ?000' when p_load is low so that the lvpecl compatible f out outputs are as jitter-free as possible. any active signal on the test output pin will have detrimental affects on the jitter of the pecl output pair. in normal operations, jitter specifications are only guaranteed if the test output is static. the serial configur ation port can be used to select one of the alternate functions for this pin. most of the signals available on the test output pin are useful only for performance verification of the MPC9230 itself; however, the pll bypass mode may be of interest at the board level for functional debug. when t[2:0] is set to 110 the MPC9230 is placed in pll bypass mode. in this mode the s_clock input is fed directly into the m and n dividers. the n divider drives the f out differential pair and the m counter drives the test output pin. in this mode the s_clock input could be used for low speed board level functional test or debug. bypassing the pll and driving f out directly gives the user more control on the test clo cks sent through the clock tree. ta b l e 1 2 shows the functional setup of the pll bypass mode. because the s_clock is a cmos level, the input frequency is limited to 200 mhz. this means the fastest the f out pin can be toggled via the s_clock is 50 mhz as the divide ratio of the post-pll divider is 4 (if n = 1). note that the m counter output on the test output will not be a 50% duty cycle. table 11. output frequency range for f xtal = 16 mhz n f out output frequency range for t a = 0c to 70c output frequency range for t a = ?40c to 85c f out step 1 0 value 0 0 2 m 200 ? 400 mhz 200 ? 375 mhz 1 mhz 0 1 4 m 2 100 ? 200 mhz 100 ? 187.5 mhz 500 khz 1 0 8 m 4 50 ? 100 mhz 50 ? 93.75 mhz 250 khz 1 1 1 2 ? m 400 ? 800 mhz 400 ? 750 mhz 2 mhz table 12. test and debug configuration for test t[2:0] test output t2 t1 t0 0 0 0 14-bit shift register out (1) 1. clocked out at this rate of s_clock. 0 0 1 logic 1 0 1 0 f xtal 16 0 1 1 m-counter out 1 0 0 f out 1 0 1 logic 0 1 1 0 m-counter out in pll-bypass mode 1 1 1 f out 4 table 13. debug configuration for pll bypass (1) 1. t[2:0]=110. ac specifications do not apply in pll bypass mode. output configuration f out s_clock n test m-counter out (2) 2. clocked out at the rate of s_clock (2 ? n).
MPC9230 revision 8 march 29, 2010 10 ?2010 integrated device technology, inc. MPC9230 data sheet 800mhz low voltage pecl clock synthesizer figure 4. serial interface timing diagram power supply filtering the MPC9230 is a mixed analog/digital product. its analog circuitry is naturally susceptible to random noise, especially if this noise is seen on the power supply pins. random noise on the v cc_pll pin impacts the device characteristics. the MPC9230 provides separate power supplies for the digital circuitry (v cc ) and the internal pll (v cc_pll ) of the device. the purpose of this design technique is to try and isolate the high switching noise digital outputs from the relatively sensitive inter nal analog phase-locked loop. in a controlled environment such as an evaluation board, this level of isolation is sufficient; however, in a digital system environment where it is more difficult to minimize noise on the power supplies, a second level of isolation may be required. the simplest form of isolation is a power supply filter on the v cc_pll pin for the MPC9230. figure 5 illustrates a typical power supply filter scheme. the MPC9230 is most susceptible to noise with spectral content in the 1 khz to 1 mhz range. theref ore, the filter should be designed to target this range. the key parameter that needs to be met in the final filter design is the dc volt age drop that will be seen between the v cc supply and the MPC9230 pi n of the MPC9230. from the data sheet, the v cc_pll current (the current sourced through the v cc_pll pin) is maximum 20 ma, assuming that a minimum of 2.835 v must be maintained on the v cc_pll pin. the resistor shown in figure 5 must have a resistance of 10?15 ? to meet the voltage drop criteria. the rc filter pictur ed will provide a broadband filter with approximately 100:1 attenuat ion for noise whose spectral content is above 20 khz. as the noi se frequency crosses the series resonant point of an individual capacitor, its overall impedance begins to look inductive and thus increases with increasing frequency. the parallel capacitor combination shown ensures that a low impedance path to ground exists for frequencies well above the bandwidth of the pll. generally, the resistor/capacitor filter will be cheaper, easier to implement and provide an adequate level of supply filtering. a higher level of attenuation can be achieved by replacing the resistor with an appropriate valued inductor. a 1000 h choke will show a significant impedance at 10 khz frequencies and above. because of the current draw and the voltage that must be maintained on the v cc_pll pin, a low dc resistance inductor is required (less than 15 ? ). figure 5. v cc_pll power supply filter layout recommendations the MPC9230 provides sub-nanosecond output edge rates and thus a good power supply bypassing scheme is a must. figure 6 shows a representative board layout for the MPC9230. there exists many different potential board layouts, and the one pictured is but one. the important aspe ct of the layout in figure 6 is the low impedance connections between v cc and gnd for the bypass capacitors. combining good quality general purpose chip capacitors with good pcb layout techniques will produce effective capacitor resonances at frequencies adequat e to supply the instantaneous switching current for the MPC9230 out puts. it is imperative that low inductance chip capacitors are used; it is equally im portant that the board layout does not reintroduce all of the inductance saved by using the leadless capacitors. thin interconnect traces between the capacitor and the power plane should be avoided, and multiple large vias should be used to tie the capacitors to the buried power planes. fat interconnect and large vias will help to minimize layout induced inductance and thus maximize the series resonant point of the bypass capacitors. note the dotted lines circling the crystal oscillator connection to the device. the oscillator is a series resonant circuit, and the voltage amplitude across the cr ystal is relatively small. it is imperative that no actively switch ing signals cross under the crystal, as crosstalk energy coupled to thes e lines could significantly impact the jitter of the device. special attention should be paid to the layout of the crystal to ensure a stable, jitter free interface between the crystal and the on-board oscillator. although the MPC9230 has several design features to mini mize the susceptibility to power supply noise (isolated power and grounds and fully differential pll), there still may be applications in wh ich overall performance is being degraded due to system power supply noise. the power supply filter s_clock s_data s_load m[8:0] n[1:0] p_load t2 t1 t0 n1 n0 m8 m7 m6 m5 m4 m3 m2 m1 m0 m, n first bit last bit v cc_pll v cc MPC9230 c 1 , c 2 = 0.01...0.1 f v cc c f = 22 f r f = 10-15 ? c 2 c 1
MPC9230 revision 8 march 29, 2010 11 ?2010 integrated device technology, inc. MPC9230 data sheet 800mhz low voltage pecl clock synthesizer and bypass schemes discussed in this section should be adequate to eliminate power supply noise related problems in most designs. figure 6. pcb board layout recommendation for the plcc28 package using the on-board crystal oscillator the MPC9230 features a fully integrated on-board crystal oscillator to minimize system implem entation costs. the oscillator is a series resonant, multivibrator type design as opposed to the more common parallel resonant oscillator design. the series resonant design provides better stability and eliminates the need for large on- chip capacitors. the oscillator is totally self contained so that the only external component required is the crystal. as the oscillator is somewhat sensitive to loading on its inputs, the user is advised to mount the crystal as close to the MPC9230 as possible to avoid any board level parasitics. to facilit ate co-location, surface mount crystals are recommended but not required. because the series resonant design is affected by capacitive loading on the xtal terminals, loading variation introduced by crystals from different vendors could be a potential issue. for crystals with a higher shunt capacitance, it may be required to place a resistance across the terminals to suppress the third harmonic. although typically not required, it is a good idea to la yout the pcb with the provision of adding this external resistor. the resistor value will typically be between 500 and 1 k ? . the oscillator circuit is a series resonant circuit and thus for optimum performance a series resonant crystal should be used. unfortunately, most crystals are characterized in a parallel resonant mode. fortunately, there is no ph ysical difference between a series resonant and a parallel resonant crystal. the difference is purely in the way the devices are characterized. as a result, a parallel resonant crystal can be used wi th the MPC9230 with only a minor error in the desired frequency. a parallel resonant mode crystal used in a series resonant circuit will exhibit a frequency of oscillation a few hundred ppm lower than specified; a few hundred ppm translates to khz inaccuracies. in a general, computer application at this level of inaccuracy is immaterial. ta b l e 1 4 below specifies the performance requirements of the crystals to be used with the MPC9230. 1 c2 cf xtal c1 c1 = v cc = gnd = via table 14. recommended crystal specifications parameter value crystal cut fundamental at cut resonance series resonance (1) 1. see accompanying text for seri es versus parallel resonant discussion. frequency tolerance 75 ppm at 25 c frequency/temperature stability 150 pm 0 to 70 c operating range 0 to 70 c shunt capacitance 5?7 pf equivalent series resistance (esr) 50 to 80 ? correlation drive level 100 ? aging 5 ppm/yr (first 3 years)
package dimensions case 776-02 issue d 28-lead plcc package MPC9230 data sheet 800mhz low voltage pecl clock synthesizer MPC9230 revision 8 march 29, 2010 12 ?2010 integrated device technology, inc. s l-m m 0.007 (0.180) n s t k1 view s h k f s l-m m 0.007 (0.180) n s t b s l-m s 0.010 (0.250) n s t s l-m m 0.007 (0.180) n s t u s l-m m 0.007 (0.180) n s t z g1 x view d-d view s s l-m s 0.010 (0.250) n s t s l-m m 0.007 (0.180) n s t 0.004 (0.100) g1 g j c z r e a seating plane s l-m m 0.007 (0.180) n s t -t- -n- -m- -l- v w d d y brk 28 1 millimeters inches 0.050 bsc 1.27 bsc dim a b c e f g h j k r u v w x y z g1 k1 min 0.485 0.485 0.165 0.090 0.013 0.026 0.020 0.025 0.450 0.450 0.042 0.042 0.042 --- 2? 0.410 0.040 max 0.495 0.495 0.180 0.110 0.019 0.032 --- --- 0.456 0.456 0.048 0.048 0.056 0.020 10? 0.430 --- min 12.32 12.32 4.20 2.29 0.33 0.66 0.51 0.64 11.43 11.43 1.07 1.07 1.07 --- 2? 10.42 1.02 max 12.57 12.57 4.57 2.79 0.48 0.81 --- --- 11.58 11.58 1.21 1.21 1.42 0.50 10? 10.92 --- notes: 1. 2. 3. 4. 5. 6. 7. datums -l-, -m-, and -n- determined where top of lead shoulder exists plastic body at mold parting line. dimension g1, true position to be measured at datum -t-, seating plane. dimensions r and u do not include mold flash. allowable mold flash is 0.010 (0.250) per side. dimensioning and tolerancing per ansi y14.5m, 1982. controlling demension: inch. the package top may be smaller than the package bottom by up to 0.012 (0.300). dimensions r and u are determined at the outermost extremes of the plastic body exclusive of mold flash, tie bar burrs, gate burrs and interlead flash, but including any mismatch between the top and bottom of the plasitc body. dimension h does not include dambar protrusion or intrusion. the dambar protrusion(s) shall not cause the h dimension to be greater than 0.037 (0.940). the dambar intrusion(s) shall not cause the h dimension to be smaller than 0.025 (0.635).
MPC9230 revision 8 march 29, 2010 13 ?2010 integrated device technology, inc. MPC9230 data sheet 800mhz low voltage pecl clock synthesizer package dimensions case 873a-04 issue c 32-lead lqfp package page 1 of 3
MPC9230 revision 8 march 29, 2010 14 ?2010 integrated device technology, inc. MPC9230 data sheet 800mhz low voltage pecl clock synthesizer package dimensions case 873a-04 issue c 32-lead lqfp package page 2 of 3
MPC9230 revision 8 march 29, 2010 15 ?2010 integrated device technology, inc. MPC9230 data sheet 800mhz low voltage pecl clock synthesizer package dimensions case 873a-04 issue c 32-lead lqfp package page 3 of 3
MPC9230 data sheet 800mhz low voltage pecl clock synthesizer disclaimer integrated device technology, inc. (idt) and its subsidiaries reserve the ri ght to modify the products and/or specif ications described herein at any time and at idt? s sole discretion. all information in this document, including descriptions of product features and performance, is s ubject to change without notice. performance specifications and the operating parameters of the described products are determined in the independent state and are not guaranteed to perform the same way when in stalled in customer products. the informa tion contained herein is provided without re presentation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of idt?s products for any partic ular purpose, an implied warranty of merc hantability, or non-infringement of the in tellectual property rights of others. this document is presented only as a guide and does not convey any license under intellectual property rights of idt or any third parties. idt?s products are not intended for use in life support systems or similar devices where the failure or malfunction of an idt p roduct can be reasonably expected to significantly affect the health or safety of users. anyone using an idt product in such a manner does so at their own ri sk, absent an express, written agreement by idt. integrated device technology, idt and the idt logo are registered tr ademarks of idt. other trademarks and service marks used he rein, including protected names, logos and designs, are the property of idt or their respective third party owners. copyright 2010. all rights reserved. 6024 silver creek valley road san jose, california 95138 sales 800-345-7015 (inside usa) +408-284-8200 (outside usa) fax: 408-284-2775 www.idt.com/go/contactidt technical support netcom@idt.com +480-763-2056

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